(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit device. More particularly, the present invention relates to an LSI semiconductor integrated circuit device including a master slice on which a large number of CMOS gate elements are arranged.
(2) Description of the Prior Art
With an increase in the complexity of integrated circuits, a tendency to produce a great variety of products in small quantities has become pronounced in the field of logic LSI circuit devices, and as means of accomodations this requirement, a gate array method and a master slice method have been developed. According to these methods, a great number of transistors are formed on a wafer in advance, that is, a master slice is formed in advance, and a wiring mask formed according to the kind of the intended circuit device is combined with the master slice to connect the transistors and form a desired circuit. Therefore, mass production is possible in the step of formation of master slices, and the period of development of LSI device circuits can be shortened and the manufacturing cost can be reduced. Furthermore, when transistors are arranged regularly, designing can be effectively performed by using an electronic computer. That is, CAD (computer aided design) is possible. Therefore, a labor saving effect can be attained, the development period is shortened and errors are prevented.
As such a master slice, the present inventors previously proposed a master slice comprising CMOS elements arranged regularly in both the longitudinal direction and the lateral direction on a semiconductor substrate (see Japanese patent application No. 158445/77). This master slice is advantageous because the degree of freedom of wiring is remarkably increased, various logic gates such as NAND and NOR gates and flipflops can be prepared from this master slice, and the degree of integration can be enhanced.
A diffusion layer, a polycrystalline silicon film, or a wiring film of a metal such as aluminum are used for wiring in MOS LSI circuit devices. In the case of the diffusion layer wiring, a high impurity concentration layer is formed on a semiconductor substrate by diffusion and the low resistivity diffusion layer thus formed is utilized for wiring. Therefore, the position of the diffusion layer must naturally be precisely located. Furthermore, since the capacitance between the substrate and the diffusion layer is large, this wiring is not suitable for a long distance signal line. Since a polycrystalline silicon film is often used as the gate electrode of a field effect transistor, wiring using the polycrystalline silicon film is suitable when wiring is desired on an extension of the gate electrode or at a part of the gate electrode where simultaneous formation of an electrode gate and the wiring layer is possible. Wiring using a metal film, especially an aluminum film, is most frequently adopted because of a low resistivity thereof. However, this metal film readily reacts with a silicon dioxide layer which is often used as an insulating base layer, and especially when the latter is thin, insulation becomes insufficient and the resistivity of the aluminum layer per se is increased. Moreover, a high temperature heat treatment is not permissible in a case of the metal film, because the film incurs breaks while in a molten state at a high temperature. In the case of multi-layer wiring (i.e. where wiring layers are arranged as if to intersect each other and, even if they do not intersect each other, as in the case of grid wiring, longitudinal lines and lateral lines are independently laid out in a first layer and a second layer, respectively), there is adopted a method in which polycrystalline silicon is used for a first base layer and aluminum is used for a second base layer located above the first base layer. In this case, of course, the resistivity of polycrystalline silicon is higher than that of aluminum. Incidentally, in the case of multi-layer wiring, the number of layers is oridinarily two or three, and if the number of layers is increased, the base surface becomes irregular and convexities and concavities on the base become so large that breaking of lines is easily caused.